Junior FPGA Designer - Greater San Diego Area

As a Junior FPGA Designer, you will be part of a highly skilled team to design and integrate state-of-the-art algorithms on advanced hybrid DSP/FPGA platforms using the latest Altera and Xilinx FPGAs, with the specific focus on advanced wireless communication modem functions. As a team member, you will make design decisions from the ground level of bleeding-edge technologies in a startup-like environment. The ideal candidate will be someone who solves problems, takes ownership of their work, and retains a sense of urgency to meet project deadlines. We are looking for candidates with innovative and energetic personalities who are willing to innovate, explore new ideas, work well in a collaborative environment, enjoy working in small groups and are strong team players with excellent communication and interpersonal skills. 1-2 years of relevant industry related experience or equivalent university research experience involving FPGA coding with an advanced degree is required.


  • Assist in developing FPGA functional requirements, specifications and platform selections based on project requirements
  • Design and implement various FPGA interfaces and control including SPI, UART, ADCs, DACs, etc. 
  • Integrate custom and vendor IP cores as well as improve and reuse existing VHDL modules
  • Interact with radio system engineering staff to develop and verify FPGA functional requirements prior to implementation, testing and debugging of mixed signal prototypes to verify performance


  • 1-2 years of FPGA code development and design experience
  • High proficiency in all phases of FPGA code development 
  • Proficient in Modelsim simulator including testbench 
  • Proficient in tools such as Xilinx ISE and/or Altera Quartus, 
  • Outstanding communication skills
  • BSEE/BSCE (Masters preferred, Ph.D.s welcome to apply)


  • Familiarity with high speed interfaces (MGT and/or GTX)
  • Familiarity with Matlab
  • Familiarity with scripting languages (Tcl, Python, and/or Perl)
  • Knowledge of C/C++.
  • Familiarity with FEC coding (Reed-Solomon, LDPC)
  • Familiarity with either NIOS or MicroBlaze embedded processors
  • Familiarity with model based and OpenCl based FPGA design flows
  • Familiarity with SOC platforms such as Zynq
  • Familiarity with JESD204B high speed interfaces including: RTL coding (either VHDL or Verilog), place-and-routing, timing closure, and on-board debugging development especially specifying timing constraints

Type: Full-time

Experience: Junior level

Functions: Engineering, Design, Research

Industries: Research, Wireless, Defense & Space

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